A 101-dB SFDR 98.5-dB DR 20-kHz BW Continuous Time Incremental Δ∑ ADC with FIR DAC and Robust Reset Timing for Sensor Interfaces

Incremental <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ΔΣ</tex> analog-to-digital converters are highly advantageous in sensor interface integrated circuits due to its ability to minimize latency and easily multiplex signals. This makes it a great choice for sensor interface applications. In this paper, a third-order continuous time incremental ADC is proposed, which incorporates circuit techniques such as chopping, FIR DAC and robust reset timing to achieve high resolution. The ADC is prototyped in 0.18 μm technology. This work can achieve a peak SNDR of 93.7dB, SFDR of 101dB with a 2.54 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">vₚₚ</tex> input amplitude and a DR of 98.5dB, occupying an area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.197mm²</tex> . This work consumes 342.8μW with 1.8V supply voltage and 20kHz bandwidth, resulting in a Schreier Figure of Merit (FoMs) of 176.1dB. It is highly suitable for sensor interface readout systems.