Assessment of 180 nm double SOI technology for analog front-end design with back-gate voltage

This paper provides an assessment of the electrical and noise performance in the 180 nm double silicon-on-insulator (DSOI) technology, which shows advantages for analog front-end radiation detectors. For the first time, the impact of the back-gate voltage on the electrical and noise performance of DSOI MOSFETs is investigated. The transconductance-to-current ( g m / I D ) ratio and low-frequency (1/ f ) noise were measured as a function of the MOS device types (NMOS/PMOS), gate length, and bias condition of front- and back-gates. Experimental results show that positive back-gate voltage deteriorates the g m / I D ratio of the MOSFETs in weak inversion region. The DSOI NMOS devices overwhelm the PMOS with better g m / I D and 1/ f performance. The DSOI devices have a comparable 1/ f noise with the 180 nm SOI counterparts. With negative back-gate voltage applied, the low frequency noise performance of NMOS is improved. This assessment of DSOI technology gives a guideline for the readout circuit design in detector front-end systems.