In this paper, we investigate a new scheme of Cu/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> hybrid bonding utilizing Cu pads with protrusion of 5-10 nm, and demonstrate that the bonding strategy is capable to achieve low temperature and time-saving bonding for chip-to-wafer (C2W) bonding applications. To study and reveal underlying bonding mechanisms, physical and chemical characterizations of the bonding surface and interface are performed. Atomic force microscope (AFM) measurement was carried out to detect the topography and surface roughness of Cu pads and SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> dielectric. Moreover, scanning electron microscopy (SEM) and electron backscattered diffraction (EBSD) analysis are used to observe the hybrid bonding interface. The experimental results demonstrate that grain growth and recrystallization have occurred at the Cu-Cu bonding interface, and no obvious cracks or voids are found in the SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> bonding interface. It can be concluded that a reliable and seamless Cu/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> hybrid bonding is realized at the low temperature of 200℃ with the pressure of 30 MPa for 5 mins, annealing at the temperature of 300℃ for 3.5 hours.
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Fang et al. (2024) studied this question.
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