Low Temperature Cu/SiO₂ Hybrid Bonding Using Area-Selective Metal Passivation (Interface Metal) Technology for 3D IC and Advanced Packaging

This study explores important chip-level bonding structures for heterogeneous integration in microelectronics, focusing on Cu-Cu and Cu/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> hybrid bonding. Structure I investigates Cu-Cu bonding, while structure II demonstrates Cu/SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> hybrid bonding with area-selective metal passivation. The research highlights the significance of anti-oxidationġ successful bonding. Both structures use electroless plating for Ag deposition on Cu, offering advantages over traditional physical vapor deposition (PVD). Successful low-temperature bonding (decreased from 250 to 180 °C) is confirmed by SAT and SEM analyses, showing excellent bonding quality with no interface gaps. Electrical measurements on structure II reveal specific contact resistances around 2.5 x 10 −7 Ω-cm2, demonstrating the effectiveness of this method in microelectronic device fabrication and integration.