New Method of Creating Through Silicon Vias for Next Generation Packaging Techniques

As chip designs increase in complexity 3D multidie packaging is becoming more appealing as a solution to increasing the complexity of designs while maintaining high density. High aspect ratios of through silicon vias require wafer-thinning to enable high-quality metallization. Unfortunately, the removal of large amounts of silicon during wafer thinning leads to non uniformity across wafers and exacerbates sample-to-sample variation. We present an alternative metallization approach for high-aspect ratio silicon vias removing the need for wafer-thinning. We demonstrate a means of flood filling (not inkjet printer dependant) with colloidal conductive ink to overcome the challenges of high-aspect ratio metallization. Our approach yields high density vias with 20 μm via diameters, an aspect ratio of 1:19 on a 72 μm pitch and an average resistance of 36.8 mΩ.