Three-dimensional integrated circuits (3D ICs) have emerged as a key technology to sustain scaling trends in the microelectronics industry. This advancement calls for a fundamental shift in how electrical interconnects are implemented, with through-silicon vias (TSVs) playing a pivotal role in enabling vertical connectivity between stacked chips. However, the metallization of TSVs traditionally involves elaborate and demanding processes, which can limit the speed and flexibility of prototyping and design modifications. In this paper, we investigate the use of Ultra-Precise Dispensing (UPD) technology of novel silver nanoparticle-based pastes as a simple and adaptable alternative to the metallization of TSVs process. The TSV filling process is outlined, followed by a detailed analysis of their morphology, filling quality, and electrical performance. We successfully achieve filled vias through a 280 μm thick silicon substrate with diameters down to 20 μm, resulting in an aspect ratio of up to 14:1, exhibiting favorable electrical properties. This work contributes to the achievement of dense, high-aspect ratio TSV fabrication using additive manufacturing, demonstrating a path towards reduced complexity of standard technology processes cycle, lower cost potential, and increased design flexibility.
Szczotka et al. (Fri,) studied this question.