Addressing the challenges posed by high-speed data caching and transmission in the readout circuit of a GM-APD array, this paper implements a readout integrated circuit (ROIC) by adopting on-chip memory on the basis of the classical digital timing readout architecture. On-chip memory technology satisfies the data storage requirements of multi-echo with limited pixel area and improves the data frame rate. Based on the 55nm BCD process, a 32×32 array ROIC is proposed, the pixel area of the system is less than 50μm×50μm, and the maximum frame rate reaches up to 58kHz.The system can realize 350ps average time resolution under 1.28μs detection range, with a time quantization nonlinear error |DNL|≤0.25LSB, |INL|≤0.4LSB; Under 25% photon detection probability, the average power consumption per frame is measured around 236mW.
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Wu et al. (2024) studied this question.
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