System Level Analysis and Design Optimization of Back-side Power Delivery Network for Advanced Nodes

Recently, the semiconductor industry has made much progress since the development of the first transistor in 1947. As the miniaturization of semiconductor technology scaling continues, it is challenging to meet the target of low loss power delivery network (PDN) specification. Thus, in order to solve these issues, a new technology called back-side PDN (BSPDN) has been recently introduced and developed to apply for advanced node to mitigate the increasing static IR-drop (SIR) and Dynamic Voltage Drop (DvD) risk from the conventional PDN, name as Front-side PDN (FSPDN). This paper describes three BSPDN schemes, Through Silicon Via (TSV), Via Buried Power Rail (VBPR), and Back-side Contact (BC) schemes, which are categorized by the connecting method from BSPDN to the active device. From the comparison of FSPDN and 3 BSPDN schemes in terms of SIR and DvD, the BC scheme which is directly connected to the active device has the less drop; only 40% in the worst SIR and 16% of the worst DvD values which came from FSPDN drop results. Based on the on-chip level SIR and DvD analysis of BSPDN, an additional experiments and analysis are performed in system-level which includes the resistance and inductance model of package bump. Through the system-level analysis, the worst DvD value can be reduced up to 47.2% of FSPDN without package. In addition, from the variation of the package models, the worst DvD of BSPDN can be reduced up to 35.5% of FSPDN without package. Consequently, the BSPDN is an effective solution of advanced nodes to improve IR and DvD drop mitigation with the co-optimization between on-chip PDN and system.