Backside power delivery as a thermal remedy for buried-oxide self-heating in 3 nm complementary Forksheet CMOS

As gate-all-around (GAA) architectures push the CMOS roadmap into the 3 nm node and beyond, the volume available to conduct heat away from the active channel shrinks faster than the power density falls. In the forksheet a lateral fusion of the n- and p-nanosheet stacks separated by a thin dielectric wall the problem is aggravated by the buried oxide (BOX) that traditionally isolates the device from its handle wafer, because silicon dioxide is roughly two orders of magnitude less thermally conductive than the silicon and metal that surround it. In this work we quantify, using three-dimensional electrothermal technology computer-aided design (TCAD), how strongly the BOX throttles heat removal in a 3 nm complementary forksheet, and we evaluate backside power delivery (BSPDN) as a structural remedy. A single, geometrically consistent device Lg = 12 nm, three 7 nm sheets, a 17 nm SiO 2 wall is characterized across a BOX-thickness sweep of 0–10 nm, extended to 50 nm to establish the thick-oxide limit, and against a BSPDN implementation in which the buried oxide and silicon handle are replaced by degenerately doped silicon power columns feeding buried copper rails. Thermal transport in the 7 nm sheets uses a first-principles, size-corrected silicon thermal conductivity rather than the bulk value. Quantum confinement in the thin sheets is captured throughout with the Hänsch modified-local-density-approximation (MLDA) correction, which we found to be markedly more robust than the density-gradient and Bohm quantum-potential schemes for this metal-rich three-dimensional geometry. The peak lattice temperature rise increases monotonically with BOX thickness, from 80 K at 0 nm to 294 K at 10 nm at a fixed drain bias of 0.75 V; the corresponding self-heating thermal resistance rises from 5.9 × 10 5 to 2.31 × 10 6 K W −1 . The BSPDN device, by contrast, exhibits a thermal resistance of 1.07 × 10 6 K W −1 a 40% reduction relative to a 6 nm BOX and 54% relative to a 10 nm BOX while leaving the transfer characteristics (threshold voltage, subthreshold swing, DIBL) essentially unchanged, confirming that the benefit is thermal rather than electrostatic. A set of BSPDN design levers is then quantified: widening the copper rail toward the device lowers the thermal resistance further to 8.7 × 10 5 K W −1 , though it remains above the oxide-free reference, substituting tungsten for copper costs 9%, and each nanometre of residual backside dielectric adds roughly 1.9 × 10 5 K W −1 . At the circuit level, a self-heated CMOS inverter built from the same device runs 36 K above ambient with the BOX backside but only 11 K with BSPDN. The study provides a physically transparent, quantitatively grounded case for treating backside power delivery as a co-optimized thermal-and-electrical technology rather than a purely routing-driven one.