Exploration of Network Interface Architectures for a Real-Time Network-on-Chip

Network interfaces play a central role in multicore architectures that use a network-on-chip for communication. Network interface designs have not received much attention in the research community despite this central role.This paper explores different network interface configurations for a real-time network-on-chip architecture. We evaluate the effects of different FIFO queue organizations on the bandwidth and maximum latency of messages in a time-division multiplexing network-on-chip.