Design of Educational Model of 4-Bit Multiplier

In the paper we design of the teaching model of the 4-bit multiplier. In the beginning of paper, we will show how to create a mathematical model of a full adder, which is necessary for the operation of the multiplier. We will represent the basic model of the full adder and more reliable version of full adder. We will compare the reliability of the individual logic elements from which is the full adder made and subsequently show how to create a n-bit full adder. Using an example, we will show how to multiply two binary numbers and based on the solution procedure of the example, we will propose a logical model of a 4-bit multiplier. Finally, we measure propagation delays on the physical model of a 4-bit multiplier.