Simulation study demonstrates reduced latency in a 4×4 array multiplier using transmission gate full adders, highlighting performance gains over semi-dynamic CMOS logic.
Multiplication is the most essential function carried out by the arithmetic and logic unit. The multiplier specifically has important applications in signal processing analysis, image processing analysis, and so on. The design of multipliers with high-performance properties such as fast speed, low power, small size, and minimal latency is of great interest in the research field. In this research, a 4×4 array multiplier using a transmission gate full adder has been designed. The full adder used in the design is a conventional CMOS full adder implemented using XOR, AND, OR gates with a load capacitance of 32F. In the architecture, the same 4×4 multiplier has been designed using semi-dynamic logic and has carried out different design parameters calculations and observations respectively along with process, voltage, and temperature variation (PVT) of 10%. When compared to Full Adder implementation using a semi-dynamic logic gate, Full Adder implementation utilizing a transmission gate imparts less latency. Each of the mentioned logic blocks is designed using LT-Spice software for 180nm technology.
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Rathore et al. (2024) studied this question.
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