Design and Analysis of 4 Bit Multipliers Using Pass Transistor Logic and Gate Diffusion Input Technique Using 18nm FinFET Technology

Very Large-Scale Integration (VLSI) is a method for manufacturing integrated circuits, where an extensive number of transistors are intricately placed onto a single silicon chip. Complementary Metal Oxide Semiconductor (CMOS) stands out as a leading technology in computer chip design, while Pass-Transistor Logic (PTL) serves as a prevalent logic design technique, utilizing transmission gates or pass transistors instead of traditional inverters for logic gate implementation. The Gate Diffusion Input Technique (GDI) is known for speed and power efficiency. A <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4× 4</tex> array multiplier (AM) using Ripple-Carry Adder (RCA) finds applications in digital signal processing and computing, particularly in tasks like digital filtering, signal compression, image processing, and video processing. The speed of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4× 4</tex> AM using RCA is slower than the other multiplication methods that incorporate Carry-Look Ahead Adder (CLA). This work involves the design of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4× 4</tex> AM using FinFET technology with PTL logic. The parameters like propagation delay, power, and power delay product for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4× 4</tex> AM is estimated using the CADENCE Virtuoso Tool at 18nm technology node with a supply voltage of 1.8V. The existing AM using RCA has the power consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">724.43\</tex> and propagation delay of 30.26 ns. The proposed AM using CLA with PTL logic experiences a delay of 10.10 ns and power consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">185.07\ μ W</tex> . This indicates that the proposed multiplier exhibits less delay and lower power consumption compared to other FinFET based multipliers. In addition, the proposed multiplier enables a maximum of 66.62 % improvement in speed and 79.12 % improvement in power when compared to its counterparts thereby showcasing its potential for improved efficiency in integrated circuit applications.