Design and Analysis of FinFET models based Ternary 1-bit Multiplier

The emergence of multivalue logics in the realm of digital electronics has been recognized as a significant achievement, offering remedies to the constraints imposed by binary logic. Ternary logic is regarded as a novel approach in the domain of multivalue logic. This article presents the design of a ternary 1-bit multiplier utilizing 18nm FinFET technology in Virtuoso tool offered by Cadence. The performance of the multiplier is then evaluated by comparing the results obtained using the SVT and HVT models of FinFET. The obtained simulation results demonstrate power consumption as 43.18 and 38.71μW, transient delay as 30.24 and 50.29 ns, and power delay product as 1305.76 and 1946.72 (x 10 −15 J) for the SVT and HVT FinFET models, respectively. The proposed architecture of 1-bit ternary multiplier demonstrates advantages in terms of energy efficiency in computing systems and signal processing systems that utilize ternary signals.