Optimized Vedic Multiplier Using 3nm Nanosheet Technology

Nanosheet FET technology is an alternative to FinFET and CMOS technology as it gives low leakage current and low power consumption. NS-FET has better mobility and scaling compared to CMOS technology. Multiplier is an important arithmetic circuit required in many digital arithmetic applications. Area, power-efficient multiplier is the need of ALU. Vedic sutras not only reduce hardware but also improve parameters like power and delay. This paper explains the implementation of Vedic arithmetic circuits of 3 nm NS-FET technology in physical layout. The proposed designs are implemented in Micro wind EDA 3.9 with 3 nm deep submicron technology post layout. The values of model parameters are used from the current Berkeley 4 short channel model (BSIM-CMG). The performances of the Ex-OR gate, 2-bit Vedic multiplier are analyzed. Analyzed results show that the proposed I design of Vedic Multiplier shows 96.40% and the proposed II design shows 117.82% power reduction compared to the 14nm VM.