A Comparative Study of Vedic 4-Bit Multiplier Using CMOS and MGDI Technology

In this article, a Vedic 4-bit multiplier is intended using CMOS and MGDI technologies. In essence, a well performing multiplier improves the efficiency of the system. In the current digital era, a multiplier is one that uses energy while also having a very significant impact on the situation. Multiplier optimization will be important for both power and delay. Additionally, adders are crucial to the multiplier. Here, the ripple carry adder is being used. In this project, gpdk 90nm technology is used in conjunction with the Tanner EDA tool to implement the design. We execute transient results in this, considering the parameters of Area, Delay, and Maximum power.