(Invited) Advanced Compute Scaling: A New Era of Exciting, Sustainability-Aware Innovations with Nanosheet-Based Devices, Increased Interdisciplinary Synergies, and (R)Evolution Towards Higher Versatility

We report on several key elements for enabling advanced compute scaling. At transistor level, as we are entering the nanosheet (NS) era, the focus lies on single-level NSFETs consisting of several vertically stacked NS per device, which can evolve into 3D stacked configurations like the so-called complementary FET (CFET) with potentially different materials/crystal orientations for the stacked channels. New device connectivity schemes are also becoming possible thanks to the trend towards using both wafer sides, started with the move of on-chip power distribution to the wafer’s backside. As devices are becoming sandwiched and accessed from levels above and below them, that also allows interesting new opportunities for transistor engineering, some examples of which will be discussed here. In parallel, from a system level’s perspective, a (r)evolution towards smart disintegration, enabling higher flexibility and hybridized technology platforms, is expected to further allow new scaling paths, also as it can help ease the introduction of new materials and device architectures.