This paper presents a switchable self-bias polarity on the CMOS complementary cross-coupled rectifier to improve the rectifier’s power conversion efficiency (PCE) profile across a wide input power (PIN) dynamic range. This technique achieves this by adaptively switching the polarity of the bias on the n-MOS to overdrive it during low PIN to improve the sensitivity and underdrive it during high PIN to suppress the shoot-through loss and the unnecessary discharge of the coupling capacitor. The popular self-biased p-MOS is also implemented further to reduce the reverse conduction loss during high PIN. The proposed rectifier is fabricated in a 40 nm CMOS process and operates at 900 MHz with a load of 50 kΩ. The proposed rectifier achieved a peak PCE of 72.1% and maintained a 0.8xPCEPEAK across a PIN dynamic range of 11.5 dB.
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Teo et al. (2024) studied this question.
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