AES 32: An FPGA implementation of Lightweight-AES for IoT Devices

IoT is marked by the resource-constrained devices.Information security is the main challenge that arise due to wireless transmission of data by ubiquitous sensors.The rapid expansion of IoT setups with resource-constrained devices has spurred research into low-cost information security solutions.This study presents an efficient version of AES for high throughput.The AES's data path is 32-bit compressed.Implementation has been carried out on different FPGA families.Data path compression and use of BRAMs has led to improved throughput with savings in resource consumption.Loop-unrolled AES results in the consumption of 2669 slices which 12 times as big as this design.While 32-bit AES with 128-bit data path consumes 4 times more resources than proposed design which uses 223 slices and 5 BRAMs on Artix-7 FPGA.The proposed design delivers throughput in the range of 2.2 to 3.5 Gbps and achieves efficiency of 1.75 Mbps-7.8Mbps per slice on different FPGAs.It outperforms different lightweight ciphers and constrained AES implementations in existing literature.