Complete System Analysis of High Speed Serial Interfaces of Data Rate up to 20 Gbps with IBIS-AMI Models

As handheld electronic equipment becomes more compact, it also demands higher performance. To achieve the overall best performance of the system, Printed Circuit Boards (PCB) are embedding different best-suited blocks from different IP vendors. This integration often results in the use of different transmitters and receivers from different-different IP vendors within the same module. Consequently, there is a growing need for a universally accepted Computer-Aided Design (CAD) model that can support high-speed serial interfaces. This paper describes a model known as I/O Buffer Information Specifications-Algorithmic Modeling Interface (IBIS-AMI), including its generation and verification steps for a reference design and its uses in complete system analysis. The reference design used in this study is a PHY transmitter with an operating data rate of up to 20Gbps with different signal processing features like multi-level pre-cursor, post-cursor de-emphasis, multiple-level differential swing, and choices of output differential impedances. To evaluate the complete system, the IBIS-AMI model of the PHY transmitter has been used and the effects of various transmitter parameters (swing, pre-cursor, and post-cursor de-emphasis) on the overall system performance has been analyzed. This paper also discusses the results to better understand how the system behaves at various electrical settings.