Analytical Modeling of parasitic Capacitance using Complementary Field Effect Transistor (CFET)

New techniques Developed to reduce circuit level work of the devices and also benefits for the efficiency of transistors Complementary field effect transistors (CFETs) is used with stacked N-type FETs (NFETs) and P-type FETs (PFETs).By using this technique basically difference in the geometry of the design Compared to the conventional MOSFET design.To represent the inverter structure of CEET in this paper for a test model to quantify capacitances in the parasitic way.This gives benefits in terms of speed and accuracy of the circuit.For reducing parasitic capacitance in CFET-based circuit designs this model play important role.The impact of device failure on the total investment was also evaluated.The weld design model is integrated into the BSIM model and can be used for 3D TCAD simulations.The proposed model will help reduce interference in CFET device design and CFET-based power generation.