Evaluation and Optimization of GAA-CNTFET Performance for High-K Dielectric Materials

In this paper, a 14-nm Gate-All-Around Carbon Nanotube Field Effect Transistor (GAA-CNTFET) is designed and simulated using SILVACO Deckbuild's ATLAS3D simulator. First, a GAA-CNTFET is simulated using a group of single high-k dielectric materials with different electrical characteristics and dielectric constants. The thickness of the dielectric materials is 5-nm. Performance parameters like the Ion/Ioff current ratio and subthreshold slope (SS) are compared to show the pros and cons of each dielectric material. Observations show that the SS value is best for SiO2, and high-k dielectrics offers high Ion currents and a greater Ion/Ioff ratio of order 10 10 . Thus, to further enhance the device operation and performance parameters, the dielectric material is optimized to be used as a stack of SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> to combine the benefits of both dielectric materials, giving an enhanced and optimized GAA CNTFET. Using the TONYPLOT2D and TONYPLOT3D graphical and structural models of the device, desired parameters could be observed and extracted. Key findings from the paper are the GAA-CNTFET's performance improvement due to the use of stacked low-k and high-k dielectric. A foundation for the use of stacked gate dielectric material is laid, where the performance parameters can be controlled by changing the dielectric materials and their thickness in the dielectric stack.