Design of Optimized Compressor Based Multiplier with Error Correcting Module

The main concept of approximation computing is to compromise on calculation accuracy in order to increase the efficiency and performance. Inaccurate calculation is effectively tolerated in many significant applications, including multimedia signal processing and image processing applications with its exceptional energy, approximate computing can withstand soft mistakes and low accuracy that are present in many applications. By lowering the criteria for precision, it can result in significant reductions in circuit complexity, latency, area, and energy usage. In contrast to the conventional multiplier, our proposed approximation multiplier design uses the Dadda multiplier and modified partial product to show smaller area and shorter critical path time. Xilinx is used to examine the suggested design in order to evaluate the performance of the multiplier.