April 23, 2024IEEE Transactions on Circuits & Systems II Express Briefs

3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction

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Integrated jitter decreases significantly when implementing a direct correction path, overcoming phase frequency detector latency in digital phase-locked loops.
Integrated jitter drops to 942 fs from 1231 fs in the prototype, while preserving baseline reference spur levels during high-frequency clock generation.
Realized in 40-nm CMOS technology, the architecture applies an adaptive pulse width controller to optimize proportional gain alongside direct loop latency correction.

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Implication

Prototype evaluation demonstrates 25% lower integrated jitter in 40-nm digital phase-locked loops, highlighting effective direct-path latency mitigation.

Cite This Study

Park et al. (2024) studied this question.

synapsesocial.com/papers/68e6e098b6db64358765c1f6 https://doi.org/10.1109/tcsii.2024.3392771

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Implication

Prototype evaluation demonstrates 25% lower integrated jitter in 40-nm digital phase-locked loops, highlighting effective direct-path latency mitigation.

3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction

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Implication

Cite This Study

3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction

Key Points

Discussion

Implication

Cite This Study

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