Machine Learning Based Static and Dynamic Error Calibration in Data Converters

This work presents a supervised machine learning (ML) technique to simultaneously suppress static and dynamic errors in successive approximation register (SAR) analog-to-digital converter (ADC) and a delta-sigma digital-to-analog converter (DAC). Capacitor mismatches, reference ripple and kick-back errors in switched-capacitor circuits, and element mismatch and inter-symbol interference (ISI) errors are the sources of static and dynamic errors in SAR ADC and Δ Σ DAC respectively. Conventional approaches employ dynamic element matching, error-shaping and high-speed reference buffers for suppressing these errors at the cost of increased power/area penalties and complex design efforts. The proposed ML approach uses a supervised technique in which a low-speed SAR ADC is used for learning and correcting dynamic errors digitally in both ADC and DAC using a single on-chip ML circuit. The key advantages of the proposed approach are - detailed knowledge of error generation mechanisms are not needed for calibration, reduction in power consumption and improvement in data converter performance.