Power-up Self Auto Calibration of High Speed SAR Converter in a 22nm FD-SOI CMOS Process

Test and reliability are important aspects of high-quality chip manufacturing which can introduce a noticeable level of cost to the final silicon products. Hence, reducing the amount of required steps and even more significantly the correction actions during tests through self-calibration is valuable. This work proposes an auto power-up self-calibration technique for a Successive-Approximation (SAR) Analog to Digital Converter (ADC) in a 22nm FD-SOI CMOS Process. By removing the two most dominant error sources in the design during the power-up, only a quick single DC test is left to manufacturing process. The idea involves calibration of the two independent error sources one at a time and hence resulted in 9.53-bit ENOB performance at 4 times Nyquist bandwidth during extracted simulations. The back-gate of the FDSOI process devices were utilized as a tuning knob in the proposed calibration scheme without introducing any extra load in the signal path of the circuit.