Sequential Decoders for Binary Linear Block ECCs

This paper proposes a simple sequential decoder architecture for relatively strong ECCs with the goal to reduce the complexity and latency of error correction in memory and storage systems. Given an ECC able to correct a maximum of t erroneous bits per code word, up to $t-1$ erroneous bits are handled within one decoding cycle as with a single-cycle fully-combinational decoder. Additional cycles are introduced only in the presence of t erroneous bits in order to implement a so called step-by-step decoding. This may facilitate a reduction of the decoder latency with negligible decoding (clock) cycle overhead. Further logic optimization is achieved based on the exploitation of observability and controllability don't cares resulted from the utilization of oversized syndromes. The application to triple-error-correcting BCH codes $(t=3)$ enabled up to 22% latency and 45% logic area reductions as compared to single-cycle fully-combinational decoders.