A Leakage Analysis Methodology Considering Intra-Cell and Inter-Cell Layout Dependent Effect

With the technology continuously scaling down, chip leakage becomes a crucial spec especially for mobile and IOT products. However, due to IC fabrication's process complexity dramatically increasing, more and more layout dependent effects are beyond pre-silicon standard cell library characterization coverage. It brings uncertain gap to post-silicon leakage over spec risk or pre-silicon over design burden. This paper presents a methodology for digital logic IP level leakage analysis. The proposed method considers both intra-cell and inter-cell layout dependent effect, together with cell physical abutment information, to predict IP leakage. It is a systematic way that can be used to reduce more than 10% leakage gap between pre-silicon estimation and post-silicon measurement especially for mixed-Vt digital design.