Design of PnR Flow For Block Level Chip for Optimizing Leakage Power

To satisfy the future requirements of chip design, modifications must be made to software/hardware capabilities, design tools, and procedures. Engineers developed an efficient structured ASIC chip architecture to make these changes while concentrating on the design characteristics. ASIC design cycle that is mature and silicon-tested consists of several stages, including designconception, leakage power optimization, logical/physicalimplementation, design validation, and design verification. In this project we figured out several techniques to optimize leakage power. That includes using of LVT, HVT and Multi-threshold voltage cells in the placement and routing stage. Later we observed that a significant figure of leakage power has been reduced i.e. from 6.29e+05 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> 5.39e+05 n W.