Triple Self-Aligned Split-Gate Architecture for High-Speed Applications of 4H-SiC VDMOSFETs

A 1700- V -class 4H-SiC VDMOSFET featuring a simultaneously triple-self-aligned channel, JFET region, and split-gate architecture <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(SA³)</tex> for high-frequency switching performance is proposed for the first time. The dc and ac characteristics of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SA³</tex> VDMOSFET are compared with non-self-aligned versions through intensive simulation. Both the dc and ac characteristics of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SA³</tex> VDMOSFET are significantly improved because of its symmetric structures and low parasitic capacitance. The gate charge, switching delay, and input capacitance of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SA³</tex> VDMOSFET are improved 33%,50%, and 17%, respectively, versus those of a worst-case non-self-aligned VDMOSFET.