A Novel Asymmetric Trench SiC MOSFET With an Integrated JFET for Improved Reverse Conduction Performance

In this article, a 1200-V asymmetric trench (AT) silicon carbide (SiC) metal–oxide–semiconductor field effect transistor (MOSFET) with an integrated junction field effect transistor (JFET) is proposed with improved cut-in voltage ( <tex-math notation="LaTeX">Vcut-in </tex-math> ) and switching loss. For the proposed device named IJ-ATMOS, the bottom p-well in contact with the source can deplete the surrounding current spreading layer (CSL) region, so the JFET channel (JFET-C) is normally- OFF when device is in forward operation. In addition, the source is in contact with CSL. Due to a smaller potential barrier, <tex-math notation="LaTeX">Vcut-in </tex-math> of this path is lower than the p-n body diode. Therefore, the intrinsic body diode is fully inactivated and the bipolar degradation is eliminated. Meanwhile, the gate to drain charge ( <tex-math notation="LaTeX">Qgd </tex-math> ) and switching loss are reduced by using the split gate MOSFET structure. Through TCAD simulation, the IJ-ATMOS decreases <tex-math notation="LaTeX">Vcut-in </tex-math> by 50.35% compared to the conventional AT SiC MOSFET (C-ATMOS). The <tex-math notation="LaTeX">Qgd </tex-math> and the switching loss are decreased by 14.29% and 30.61%, respectively.