Fabricating and TCAD Optimization for a SiC Trench MOSFET With Tilted P-Shielding Implantation and Integrated TJBS

In this article, we proposed and fabricated a prototype of single-channel SiC trench MOSFET with integrated trench junction barrier Schottky (TJBS) on the trench side for 1200-V application, named TJBS-MOS. The TJBS is protected by the grounded <tex-math notation="LaTeX">P⁺ </tex-math> shielding layers under the gate and trench bottom. The measured specific ON-resistance ( <tex-math notation="LaTeX">RON,sp </tex-math> ) is 5.95 <tex-math notation="LaTeX">mΩ · </tex-math> cm2, with reverse conducting ON-state voltage <tex-math notation="LaTeX">V_R_ ON </tex-math> = 2.6 V at 300 A/cm2, which is reduced by 2.0 V compared with that of the CoolSiC MOSFET. Utilizing TCAD calibration according to the measured results, optimized results show that for the 1200-V-rated TJBS-MOS, <tex-math notation="LaTeX">RON,sp </tex-math> of 2.52 <tex-math notation="LaTeX">mΩ · </tex-math> cm2 with <tex-math notation="LaTeX">V_R_ ON </tex-math> = 2.04 V at 300 A/cm2 is obtained. Due to reduced channel density, <tex-math notation="LaTeX">RON,sp </tex-math> is increased by 24.8% compared to a CoolSiC MOSFET with the same design rules. Fortunately, a high-frequency figure of merit (HFFOM1: <tex-math notation="LaTeX">RON,sp × CGD </tex-math> and HFFOM2: <tex-math notation="LaTeX">RON,sp × QGD </tex-math> ) are improved by 57.2% and 72.9%, respectively, owing to smaller <tex-math notation="LaTeX">CGD </tex-math> and <tex-math notation="LaTeX">QGD </tex-math> . Combined with reduced reverse recovery charge for the unipolar TJBS, the turn-on loss ( <tex-math notation="LaTeX">EON </tex-math> ) and the turn-off loss ( <tex-math notation="LaTeX">EOFF </tex-math> ) at 25 °C are reduced by 32.8% and 80.7%, respectively. Moreover, under high temperatures, <tex-math notation="LaTeX">EON </tex-math> of the CoolSiC MOSFET increases significantly, while <tex-math notation="LaTeX">EON </tex-math> of the TJBS-MOS remains unchanged.