Enhanced Charge Transfer Efficiency Using Ring Vertical Transfer Gates in Backside Illuminated CMOS Image Sensor

In this work, we have simulated, compared and reported the charge transfer efficiency (CTE), full well capacity (FWC) and image lag performance of CMOS image sensors with configurations of single vertical transfer gate (SVTG), dual vertical transfer gate (DVTG), circular ring vertical transfer gate (CRVTG), and rectangular ring vertical transfer gate (RRVTG). Our designed CRVTG and RRVTG show superior performance on all the metrics of CTE, image lag and FWC. The higher electrostatic control over the channel region between photodiode (PD) and floating diffusion (FD), enabled by CRVTG and RRVTG, lowers the channel's potential barrier, and results in better performance of the above matrices. CRVTG and RRVTG can achieve 100% CTE with PD doping <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(ND,PD)</tex> of 1E+17 cm −3 and with vertical transfer gate voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(V VTG)</tex> of 1.8 V and 1.6 V, respectively. In contrast, CTE remains non-ideal even with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VV T G=2.6</tex> V for SVTG and DVTG structures.