A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUT Augmentation

Efficiency and load capacity are critical for stable computing system operation. To address the need for compact integration and scalability, miniaturized power modules with integrated power devices in chip-sized packages are essential. These modules reduce component count and board space while maintaining high conversion efficiency and scalability for varying system loads. This work introduces a reconfigurable switched-capacitor (SC) hybrid converter topology designed for system-in-package (SiP) power modules. The DC-DC module, featuring a single inductor and capacitor directly mounted over the silicon die, achieves an enhanced output current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(lOUT)</tex> to inductor current <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(lL,DC)</tex> ratio of up to 2. It provides a continuous adjustable voltage conversion ratio (VCR) range, generating 0.4 to 1.5V output at 1.8V input, with 96.7 % efficiency and the capability to deliver 2.5A with a single module. Interleaving three modules achieves 94.3% efficiency with a maximum 6A <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</tex> <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</inf> , and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Δ VOUT</tex> reduction up to 60% through intrinsic properties of output capacitance ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</tex> <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</inf> ) augmentation. In addition, a fully integrated gate driving scheme utilizing an on-chip high-frequency charge pump (QP) and globally shared bootstrap capacitor ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</tex> <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BST</inf> ) is proposed to generate domain-floating rails catering to gate voltage demands.