A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC–DC Converter With Inherent Current Equalization Characteristics

This article presents a highly integrated hybrid dc–dc converter with a 24-V input, employing the interleaved-inductor multiple step-down (IL-MSD) topology. The proposed design ensures symmetric power-stage operations, addressing inductor current ( <tex-math notation="LaTeX">IL</tex-math> ) imbalance without complex regulation control. It also optimizes current distribution among internal conduction branches, reducing conduction losses and input capacitor requirements. In addition, we propose an on-chip gate-driving scheme utilizing a high-voltage (HV) floating current (HVFC) source and HV charge storage technique, eliminating external bootstrap capacitors and extra HV supplies. Fabricated in a 180-nm BCD process, the converter chip integrates all-N-type power switches, gate drivers (GDs), startup/pre-charge circuits, and control blocks within a 4.7-mm <tex-math notation="LaTeX">²</tex-math> footprint. Using two 1- <tex-math notation="LaTeX">μ</tex-math> H compact inductors and four 1- <tex-math notation="LaTeX">μ</tex-math> F flying capacitors, the converter regulated a 1–3.5-V output from a 24-V input with a peak efficiency of 90.4% under a 1.2-A load. The maximum load current reaches 5 A with an 82% efficiency. The achieved on-chip and overall power densities are 3.51 and 0.62 W/mm <tex-math notation="LaTeX">³</tex-math> , respectively.