Power management and delivery for modern complex SoCs such as HPC and AI/ML with advanced 2.5D/3D package has become a major challenge due to rising current demands, shrinking form factors, rapid dynamic responses, and high efficiency across various loading conditions. FIVR and SCVR [1] employ package inductors and high-density MIM capacitors to achieve high current density and vertical power delivery (VPD), but both rely on advanced packaging technology with high costs. Hybrid topologies like Flying Capacitor Multilevel Converter (FCML) [2]–[5] incorporates more capacitors and power switches to enhance the throughput power without incurring additional switching losses, but has poor light load efficiency and response speed [6].
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Sun et al. (2024) studied this question.
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