Design of Advanced High Performance Bus (AHB) to Advanced Peripheral Bus (APB) Bridge

The Advanced Microcontroller Bus Architecture (AMBA) has long served as the on-chip bus standard for System-on-Chip (SoC) designs, despite its inherent low performance. Within the AMBA framework, the Advanced High-performance Bus (AHB) is utilized to connect analog and digital signal processors, alongside high-performance memory controllers. Conversely, the AMBA Advanced Peripheral Bus (APB) facilitates connections to peripherals such as UARTs. Both buses are interconnected via a bridge, known as the AHB2APB Bridge, presenting a challenging proposition for the evaluation of AMBA-based systems. AMBA bus protocol, enables communication between different functional blocks or Intellectual Properties (IP), our endeavor focuses on building high-performance SoC designs. By exploiting the reusability of IP across different buses and supporting multiprocessor unit development, we strive to bridge the communication gap between high-performance AHB and low-speed APB. The simulation of the AHB2APB Bridge module, designed in Verilog HDL is conducted on the Xilinx Vivado platform. Our primary objective is to achieve high-speed pipelined data transfers while ensuring no data loss during transmission Key Words: System on chip, AHB2APB, Verilog HDL, Xilinx Vivado