Intel developed the Programmable Integrated Unified Memory Architecture (PIUMA) to address inefficiencies seen in conventional processor architectures for at-scale sparse graph analytics. PIUMA adopted co-packaged optical (CPO) modules to provide 1 TB/s/direction of network bandwidth. PIUMA fused traditional network switch logic into the compute logic to make a disaggregated switch fabric in a HyperX topology. Utilizing the latest CPO technology, PIUMA converts the on-die mesh protocol directly to the optical fabric and back to seamlessly glue together all PIUMA chips in a system into a large virtual die. Routing is done by the global address associated to each resource in the system, eliminating higher level protocols such as Ethernet or CXL. Measured silicon demonstrates a best-case latency of <46ns per connection mesh-stop to mesh-stop through the optical fabric in the first prototype which is not fully optimized. This was all combined into custom ASIC of 316mm 2 in 7nm manufacturing and advanced packaging technology to enable the direct CPO fabric requirements.
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Howard et al. (2024) studied this question.
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