Toward the Understanding on Threshold Voltage Drift Mechanisms in GaN MOSc-HEMTs Through the Influence of Device Architecture

In this article, the impact of device architecture on threshold voltage <tex-math notation="LaTeX">VTH</tex-math> instabilities during OFF state operation under a high drain voltage stress on GaN-on-Si MOSc HEMTs is thoroughly investigated. Measurement-stress–measurement high-voltage bias temperature instability (HVBTI) technique using ultrafast <tex-math notation="LaTeX">VGS</tex-math> ramp was used in this study. This measurement technique was carried out on various gate length ( <tex-math notation="LaTeX">LG</tex-math> ), ohmic length ( <tex-math notation="LaTeX">LOHM</tex-math> ), and field plate (FP) length. HVBTI transients performed at different <tex-math notation="LaTeX">LG</tex-math> highlight that increasing the gate length induces a better electrostatic control under the gate via a gate shielding. TCAD simulations support the claim that the relaxation peak is linked to the charge redistribution of ionized <tex-math notation="LaTeX">CN</tex-math> (-) traps under the gate. This charge redistribution during the relaxation phase is enhanced using a larger ohmic contact area. The electric field at gate and source FP corners has a strong impact on ionized <tex-math notation="LaTeX">CN</tex-math> acceptor traps located in the GaN:C layer close to the gate and consequently on positive <tex-math notation="LaTeX">VTH</tex-math> degradation observed for short stress duration. Substrate biasing and TCAD simulations suggest that the <tex-math notation="LaTeX">CN</tex-math> traps' deionization and trapping in the volume of the gate oxide is related to the presence of free holes in the GaN:C layer.