Industry Presentations: Stratus High-Level Synthesis Enables Full-Flow Hardware Design Automation and Optimization

In this presentation we will explain the advantages of constructing digital hardware using Higher-Level Languages such as C++/SystemC, or MathWorks MATLAB-code. These higher-level models are synthesized directly to Hardware using the full Cadence Digital Implementation Solution. We will delve into the design space exploration and optimization and explain how the Cadence Stratus HLS technology along with Logic-Synthesis (Genus), RTL Power Analysis (Joules), Equivalence Checking (Jasper), and Machine Learning (Cerebrus) can produce optimal production quality hardware and dramatically decrease the design implementation cycle. As a result, the overall design Power, Performance, and Area are optimized while significantly shortening the project Schedule at the same time.