Leakage Reduction on Universal Gates Using ONOFIC Technique

In order to meet the growing demand for energy-efficient digital systems, this study explores the crucial problem of leakage current in VLSI circuit design with an emphasis on low-power solutions. The increase in the number of battery-operated gadgets, wireless communication systems, and multifunctional electronics highlights the necessity for creative ways to reduce leakage power in CMOS devices. Power efficiency has become a critical consideration alongside the traditional concerns of performance, area, and cost. In order to reduce leakage current, the study presents a unique circuit-level methodology called ONOFIC (On/Off logIC), with a focus on its application to common universal gates such as NAND and NOR. The integration of a logic circuit between the pull-up and pull-down networks effectively manages leakage current in both active and standby modes, as demonstrated by the ONOFIC technique. The design of two-input NAND and NOR gates serve as an example of the approach, demonstrating notable power consumption savings over traditional designs. According to the experimental findings, the ONOFIC approach reduces leakage power for NAND and NOR gates by 85.08% and 73.66%, respectively. This research contributes new perspectives to the ongoing discourse on robust and efficient VLSI circuit design, offering promising strategies to enhance energy efficiency in digital circuits. The results continue the search for lower leakage power in advanced technology nodes by pointing to possible uses in a variety of combinational and sequential circuits.