Investigation of Wafer Warpage Evolution Baesd on Fan-Out Chip-first Process

The warpage performance of the fan-out wafer for chip-first processes is investigated by the finite element modeling in this study. In the modeling framework, which including the element birth-and-death technique for molding material removal and effective properties calculated for the copper layers of RDL, is used to determine the warpage evolution at different process stages. The developed FE simulation method can well describe the wafer process warpage. Therefore, the effect of different structure dimensions on wafer warpage prediction can be conducted.