Low Power and Enhanced Data Retention Time in DRAM in FinFET Technology

Modern technologies require huge amounts of storage space and fast access to data for uninterrupted high-quality audio and video processing. Random Access Memory (RAM) operates at higher frequencies and allows the CPU to access the files faster. It stores frequently required data so that it can be retrieved rapidly. RAM cells are classified into SRAM and DRAM. For storage SRAM cell uses two cross-coupled inverters and DRAM cell uses a capacitor. SRAM cells are more reliable but require more than 6 transistors for its storage, which consumes more area and power than the DRAM cell, where it uses less than 4 transistors for its storage. But DRAM suffers from frequent refresh issues, due to leakage across the capacitor. The leakage current is reduced to minimize the frequent refresh issue and for that several leakage reduction techniques are incorporated to design the DRAM cell to enhance the Data Retention Time (DRT). Modified Self Controllable Voltage Level Circuit (MSVL) based DRAM cells are proposed in this project. MSVL 3T and 4T DRAM cells have less leakage power and better hold performance than the conventional, Sleepy Keeper and SVL based DRAM cells. Various parameters such as dynamic power, leakage power, retention time and delay are measured and compared with other DRAM cells. 18 nm FinFET technology is designed using the CADENCE Virtuoso Tool. The proposed DRAM cell has superior hold performance than previous designs, according to simulation findings. The frequent refresh rate has been reduced and finally the power consumed due to it has also been minimized.