Electrical-Thermal Multiphysical Analysis of On-Chip Power Grid

This is the authors' abstract. We don't add key points for this paper.

With the continuous development of three-dimensional integrated circuits (3D ICs), the size of three-dimensional interconnection lines is decreasing, integration is increasing, and functionality is becoming more diverse. However, this progress is accompanied by a gradual increase in power consumption, leading to elevated temperatures of interconnection lines. High temperatures and significant temperature gradients can give rise to reliability issues in integrated circuits, resulting in degraded electrical performance of devices, accelerated aging, shortened lifespan, and even the outright failure of devices. This paper, starting from the heat conduction equation and incorporating third-kind thermal boundary conditions, analyzes the electro-thermal coupling effects of on-chip power grids. The study aims to provide insights into the impact of temperature on the performance and reliability of integrated circuits, contributing to the understanding and mitigation of thermal challenges in advanced three-dimensional integration.