Side and Corner Region Non-Uniformities in Grown SiO₂ and Their Implications on Current, Capacitance and Breakdown Characteristics

This paper addresses the correct analysis of electrical data from devices with gate oxides 20 nm that mimic those used in high voltage periphery devices of 3D NAND flash. Thick oxides grown on an active-Si region surrounded by shallow trench isolation are found to be thinner at the side and corner regions leading to contradictory electrical observations. We introduce a model where the gate oxide is divided into three different regions with different equivalent oxide thicknesses. This provides a simple way to explain the apparently conflicting electrical data and emphasizes the role of side and corner oxide regions in leakage and breakdown. By applying the model to different oxide growth processes, we also provide guidelines to limit oxide thickness variations.