Statistical Characterization of Off-State Stress Degradation in Planar HKMG nFETs Using Device Arrays

We use dedicated transistor arrays to study the impact of off-state stress degradation on scaled HKMG nFETs. By extracting several key transistor parameters across different stress <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VDS</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VGS~ 0\ V</tex> biases, we analyze the interplay between the different mechanisms involved in off-state stress degradation, namely hole injection into oxide traps and creation of interface traps. By considering diverse conventional <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vₜₕ- extraction</tex> techniques and a compact-model-based approach, we show that different methods can lead to apparently contradictory results, particularly when transistor parameters such as SS or <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</tex> are also affected by the degradation. Finally, we study the localization of the degradation mechanisms by means of forward and reverse measurements of the saturation current. These show that interface trap generation is largely localized at the drain side, while hole injection displays a less localized position along the channel.