Circulating Currents Suppression PWM Strategy for Paralleled Inverters Based on Common Mode Voltage Reduction

This paper proposes a modified Space Vector Pulse Width Modulation (SVPWM) strategy that reduces common-mode voltage and suppresses circulating currents in three-phase paralleled voltage source inverters (VSIs). The strategy is proposed based on zero common-mode voltage control algorithm and control algorithm without zero voltage vector. Zero voltage vectors are replaced with a group of opposite active voltage vectors, which reduces the action time of phase voltage difference and suppresses zero-sequence circulating current (ZSCC). PWM sequences in the same phase are exchanged in some sectors of the two inverters to eliminate differential-mode circulating current (DMCC). This strategy reduces common-mode voltage and circulating current without requiring additional hardware, making it applicable to paralleled VSIs with various parameters.