An enhanced digital control loop of Boost converter in Low Power Microcontrollers

This paper investigates a customized digital control loop for a Boost DC-DC converter, employing fractional clock cycles to precisely modulate inductor current ramp-up (ton) time and ramp-down (toff) time. The approach involves generating fractional ton time from the last clock cycle of the same ton pulse by using an inverter chain as a delay element, resulting in a 15% enhancement in load current capacity at lower peak inductor currents. Additionally, it streamlines inductor negative current correction, seamlessly adapting to changes in inverter delay that impact both ton and toff times. This scheme is implemented in 180nm CMOS technology.