Optimizing Memory Performance of a Staggered and Coplanar TFT Configuration using Indium Gallium Zinc Oxide Channel and High-K Dielectric Materials

In the fast-evolving landscape of the electronics industry, it is essential to have accurate models and simulations for devices. This paper details the simulation of memory performance in Thin Film Transistor (TFT) structures utilizing various high K dielectric materials for differently configured TFT structure. The structure of the TFT significantly influences its memory performance. This paper presents a thorough comparison of the capacitance-voltage (CV) characteristics, field effect mobility (µFE), and memory behavior of the TFTs. Mobility was studied for all the developed TFT structures at different operating temperature from the ID-VG characteristics. The CV characteristics of the developed structures the gate voltage (VG) was varied from -2V to 2V by maintaining the drain and source voltage at ground potential for two different frequencies of 1 mili Hz and 1 MHz. The memory performance was studied with transient pulse applied to gate voltage while maintaining drain voltage (VD) at 0.2V and observed the shift in threshold voltage of the ID-VG characteristics for the TFT structures. It is observed that the bottom gate staggered TFT structure with SiO2 tunneling layer has a wider memory window of 6V but the shortest retention time of one year, whereas the HfO2 tunneling layer with a slight increase in the thickness of the charge trapping layer has the longest retention period of 48 years and a wide memory window of 5.3V.