A Low-Power Temperature and Process Insensitive CMOS Power Management Unit

A Power Management Unit aimed for applications requiring low consumption and area efficiency is introduced in this work. Its main goal is to deliver the desired voltage and current outputs to be used from the other circuits of the system. In this particular topology a power consumption of 591 nW is achieved along with PSRR of 25.15 dB in worst case and a dropout voltage of 0.3 V. This work is supposed to serve as a proof of concept for very low consumption design of Power Management Units and may be included in architectures that integrate advanced features, like DC-DC converters, Pulse Width Modulation mode along with complex digital control part. The proposed system is designed and simulated using the Cadence IC Suite in a TSMC 90nm CMOS process.